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1 modem reference designs the isl837030 and isl83740 broadband wireless modem reference designs support a wide range of modulation orders and symbol rates.* in both reference designs, sophisticated coding, equalization, and symbol recovery techniques are employed, resulting in robust wireless link performance. the isl837030 and isl83740 reference designs support high-capacity digital microwave radios with data rates up to 238mbps (isl83740) and 160mbps (isl837030). they provide a flexible, high performance, economical solution for fixed wireless applications. * differences between the isl837030 and isl83740 are marked in text as needed. also see release notes on page 25 . benefits ? eliminates the need to develop custom asics optimizes wireless link capacity and bit error rate (ber) performance enables rapid prototyping and compliance testing proven technology optional evaluation kit supports demo requirements, performance evaluation, and lab testing features programmable modulation both: qpsk, 8psk, 16qam, 32qam isl83740 only: 64qam, 128qam flexible data rates isl83740: up to 238mbps isl837030: up to 160mbps programmable symbol rates reed solomon (rs) encoding/decoding concatenated coding using rs and ptcm inner code fcc and etsi spectral mask compliance powerful equalization includes sample isl87060mik modulator and ISL87060DIK demodulator chip sets for development and test. complete manufacturing documentation package: bill of materials, schematics, pcba fabrication files, including gerber files. test documentation. embedded monitor and control software provides comprehensive setup and test capabilities. accepts commands in binary or ascii format. optional evaluation kit the modem pcba is mounted on an evaluation platform, allowing the modem to be set up and tested in a standard lab environment. includes vhf and l-band if interfaces and a sophisticated graphical user interface for windows ? operating systems. (isl83700eval/isl83740eval) figure 1 simplified block diagram dac lpf differential baseband outputs baseband loopback ISL87060DIK demodulator/ decoder adc lpf decimating matched filter controller async serial data data differential baseband inputs level offset flash modem digital/power connector (p2) trimdac isl87060mik modulator/ encoder modem pcba may 2002 datasheet isl837030, isl83740 fn8013.5 ? caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved commlink? is a trademark of intersil americas inc.
isl837030, isl83740 2 fn8013.5 c ontents functional description ........................ 3 modulator functions ...................... 5 1. isl87060mik modulator assp ....... 5 2.digitaltoanalogconverter(dac) ..... 5 3.lowpassfilter(lpf) .............. 5 4. rate exchange . .................. 5 demodulatorfunctions ................... 5 1.lowpassfilter(lpf) .............. 5 2.adc ............................ 5 3.fpgadecimatingfilter ............. 5 4. ISL87060DIK demodulator assp ..... 5 5. baseband loopback ............... 5 6.automaticgaincontrol(agc)........ 6 thecontroller .......................... 6 monitorandcontrolsoftware .............. 6 performancespecifications .................... 7 modem parameters ...................... 7 modulation, inner code rates, and ranges . . . 7 modulator performance specifications ....... 8 modulator input requirements .............. 8 modulator output electrical specifications ..... 8 demodulator input requirements ........... 9 demodulator input electrical specifications .... 9 demodulatorperformancespecifications .... 10 berperformance(typical) ............... 10 controllerparameters ................... 11 environmental&physicalspecifications ......... 12 physicalinterfacedefinition ................... 13 80-pin digital/power connector ............ 14 power supply signals ............... 15 m&c port signals . . ................. 15 modulator data interface signals ....... 15 demodulator data interface signals .... 16 miscellaneous signals ............... 17 reserved ......................... 17 8-pin baseband connectors .............. 18 datatimingandpacketdefinition .............. 19 modulator data input timing .............. 19 modulator packet definition ............... 19 demodulatordataoutputtiming .......... 20 demodulatorrsdatapacketdefinition ..... 20 agctiming ........................... 21 mechanical drawings ........................ 22 applications ............................... 23 support relateddocumentation ...................... 25 releasenotes ............................. 25 customer support .......................... 25 l ist of f igures 1. simplifiedblockdiagram..............................1 2. functional block diagram .............................3 3. modem printed circuit board assembly (pcba) ............4 4. acquisition/tracking range at low baud rates ...........10 5. modem pcba connectors ............................13 6. digital/power connector pin configuration ...............14 7. modulator connector pin configuration ..................18 8. demodulator connector pin configuration ...............18 9. modulator data input timing . . . .......................19 10. modulator packet definition . . . .......................19 11. demodulator data output timing .....................20 12. demodulator data packet definition ...................20 13. agctiming ......................................21 14. modem pcba mechanical dimensions (top view) ........22 15. modulator baseband interface to isl83740eval/isl83700eval platform ............................................23 16. unbalanced demodulator baseband interface, shorter runs 24 17. unbalanced demodulator baseband interface, longer runs 24 ordering information part number description isl83740ref-cd isl83740 reference design (qpsk, 8psk, 16qam, 32qam, 64qam, 128qam) isl837030ref-cd isl837030 reference design (qpsk, 8psk, 16qam, 32qam) isl837030kit-xxx kit versions supply sample chips in lots of 24 to 120, in 24-unit increments. applies to either reference design. isl83740eval isl83740 evaluation kit (qpsk, 8psk, 16qam, 32qam, 64qam, 128qam) isl83700eval isl837030 evaluation kit (qpsk, 8psk, 16qam, 32qam) isl87060mik modulator chip ISL87060DIK demodulator chip all intersil products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, software and/or specific ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is beli eved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433
isl837030, isl83740 3 fn8013.5 . figure 2 functional block diagram demodulator baseband c o n n e c t o r m o d u l a t o r b a s e b a n d c o n n e c t o r d i g i t a l / p o w e r c o n n e c t o r data input byte clock isl87060mik modulator/ encoder controller flash 512k x 16 agc dac vco async serial digital agc analog agc data output data clock idata 10 qdata 10 sample clock agc 10 idata 10 qdata 10 2-1 mux 2-1 mux 10 10 200 msps dac 200 msps dac passive lpf passive lpf q level/bal i level/bal qoffset ioffset xo clock pll fpga decimating matched filter baseband loopback 100 msps adc 100 msps adc passive lpf passive lpf trimdac 8 8 rate exchange fpga +3.3v +5v +12v -12v external sync packet sync data flag ISL87060DIK demodulator/ decoder modem pcba functional description intersil?s broadband wireless modem devices are fully integrated and support a wide range of modulation orders and symbol rates. sophisticated coding, equalization, and symbol recovery techniques are employed to enable robust wireless link performance. the complete modem printed circuit board assemblies (pcbas) with standard hardware and software interfaces enable equipment manufacturers to rapidly integrate intersil modem functionality into their system products. the isl837030 and isl83740 modem reference designs provide a flexible, high performance, economical solution for fixed wireless applications. the modem design provides an off-the-shelf solution for users interested in easily integrating a complete modem into their products. the modem pcba architecture implements a complete baseband transmit and receive function: 1. modulator function converts byte-wide parallel data, encodes and digitizes it, and generates a differential baseband analog signal. this signal can then be up-converted to any if/rf frequency the user requires. 2. demodulator function accepts a differential analog baseband signal. filters, decodes, corrects, and converts it to byte-wide digital data and clock. 3. controller incorporates everything necessary to control and monitor the modem.
functional description isl837030, isl83740 4 fn8013.5 figure 3 modem printed circuit board assembly (pcba) fpga decimating matched filter isl87060mik modulator ISL87060DIK demodulator adc dac dac trim d6 d5 fpga rate exchange d4 flash memory controller d1 d3 dac mux mux mux mux led indicators light indicators d1 controller status blinking indicates controller is functional. solid off or on indicates not functional. d3 modem ready light on indicates modem is ready to accept user commands. equivalent to the modem_rdy signal on the interface connector. d4 pll lock detect light on indicates that the modulator rate exchange has successfully locked to the interface input byte clock. d5 alarm irq light on signals active alarm condition. equivalent to the irq signal on the interface connector. d6 demod lock light on indicates that the demodulator has successfully locked to the input baseband signal.
functional description isl837030, isl83740 5 fn8013.5 modulator functions the modulator accepts byte-wide parallel data, encodes it, digitizes it, and produces a balanced analog signal output. this signal can then be up-converted to whatever rf/if frequency the application requires. it consists of four functions: 1. isl87060mik modulator assp the modulator assp provides a digital representation of a modulated analog signal. the chip accepts byte-wide ttl data and applies: energy dispersal reed-solomon forward error correction (fec) convolutional interleaving symbol generation for various modulation formats with or without convolutional coding pulse shaping tuning the digital output from the assp consists of eight 10-bit ports, four for i and four for q. each port represents at least one of four samples per symbol which requires multiplexing before it is applied to the digital to analog converter (dac). 2. digital to analog converter (dac) the dac section muxes each of the four 10-bit ports and converts them into an analog signal representation of the digital values produced by the assp. the dac samples at a minimum of four samples per symbol based on the assp?s interpolator setting. trimdacs, controlled by the processor, provide fine adjustment of the amplitude and dc offset of the i and q output signals. two of the trimdacs control the reference voltage used by the output dacs, thereby adjusting the output signal amplitude. the default setting corresponds to a zero adjustment. 3. low pass filter (lpf) the analog signal from the dac is then filtered to eliminate undesired digitizing effects. the trimdac is used to control the offset voltage of the output signal, allowing the user to adjust the balance between the i and q baseband output signals for upconverter optimization. 4. rate exchange the rate exchange function generates clocks by converting the byte-wide interface clock to an assp processing clock. it then provides the sample clocks to the dac and mux sections. the relationship between the byte clock input and the other clocks varies dramatically depending on the fec and interpolator settings within the assp. demodulator functions the demodulator accepts differential analog baseband i and q signals, then filters, decodes, corrects, and converts them to byte-wide digital data and clock. it consists of six functions: 1. low pass filter (lpf) the lpf eliminates any undesired baseband high frequency artifacts caused by the down conversion process. 2. adc the analog to digital converter (adc) provides a digital representation of the modulated baseband analog signal. it provides eight bits of data for each of the i and q channels. 3. fpga decimating filter a field programmable gate array (fpga) based decimating matched filter is provided for additional filtering based on the desired symbol rate. multiple fpga designs are required to cover the full symbol range. they are stored in the processor?s flash memory and loaded as required, based on configuration parameters. the modem automatically toggles between the fpga designs depending on the baud rate. 4. ISL87060DIK demodulator assp the demodulator assp accepts quantized baseband i and q signals and provides all necessary demodulation functions including: carrier and symbol acquisition and tracking adaptive equalization data estimation convolutional deinterleaving energy dispersal removal decoding functions, including reed-solomon decoding 5. baseband loopback the modulator baseband output can be configured to be connected to the input of the demodulator. this allows in- system functional verification of the modem. the loop-back circuit is implemented with a fully differential buffered/switch circuit. when engaged, the loop-back signals are summed with the normal i and q input signals to the demodulator. this configuration does not require that either the normal modulator i/q outputs or the normal demodulator i/q inputs be disconnected. operation is transparent to the normal loading on these interfaces. the loop-back signals are summed with the normal input signals. therefore, when loopback is enabled the system must be set to minimize the signal input from the normal demodulator i/q input path.
functional description isl837030, isl83740 6 fn8013.5 demodulator (continued) 6. a utomatic gain control (agc) the demodulator assp provides a parallel data word to be used by the agc to optimize the dynamic range of the input signal to the demodulator. the assp averages the magnitude of the input baseband signal, subtracts that from a target value, and accumulates the results. the agc value is available in either serial digital or analog form. the agc value output is proportional to the amount by which the incoming signal?s amplitude must be increased in order for its level to reach the desired target. therefore, an increase in the agc value indicates that the signal level at the input to the agc amplifier/attenuator has actually decreased. the modem operates in two different agc modes: open loop is used when there is no external agc loop implemented. closed loop is used when the modem?s agc features aretobeused. for best performance, closed loop mode is suggested. this automatically sets the demodulator input level to the optimum value. the system default is open loop mode until any agc parameter is initialized from the host. the controller the controller is a highly integrated device used to eliminate the complexities of interfacing with the intersil assps directly. it incorporates everything necessary to control and monitor the modem. the controller?s processor takes high-level commands from the user and determines what is required to configure and monitor the assps. this relieves the user from any real-time interfacing and algorithm implementation issues. theexecutablefirmwareisheldinflashmemorythatisin- circuit upgradeable. this allows the user to upgrade the code or load in a new algorithm as required via the asynchronous serial port (the monitor and control port). monitor and control software the modem pcba is configured and monitored using intersil?s embedded monitor and control (m&c) software. this software is used to set parameters such as: modulation type code rate payload rate symbolrate output level/offset agc control diagnostics ? self-test loopback alarms baseband loopback alpha (pulse shape) statistics ber evm demodulator stress phase & amplitude imbalance andmore for details, see the programmer?s reference an9935.
isl837030, isl83740 7 fn8013.5 performance specifications modem parameters modulation, inner code rates, and ranges 1 a rate of 1 is equivalent to no inner code. 2 ranges valid for internal sync (rs 255, 238). to avoid significant performance degradation, interleaving must be enabled when using concatenated coding rates (any rate other than 1). see the mdleaver command in the programmer?s reference an9935. item description symbol rate range 3.0mbaud to 42.514mbaud payload data rate range 5.6mbps to 238mbps (isl83740) 5.6mbps to 160mbps (isl837030) outer code (reed solomon) packet size (255, 238) internal sync mode only (240, 223) external sync mode only see demodulator rs data packet definition on page 20 . power consumption 18.75w maximum fec modes fec disabled, rs fec only, concatenated convolutional inner code with rs outer code pulse shape (alpha) square root nyquist, programmable (0.15 to 0.35) in 0.05 steps tx carrier tuning range 500khz, programmable in 1khz steps non-zero tuner offsets may not meet more stringent mask requirements. rx digital matched filter 32-tap root raised cosine 0.20 rolloff factor bandwidth tracks selected symbol rate modulation type inner code rate 1 payload rate range in mbps 2 symbol rate range in mbaud ascii binary ascii binary isl83740 isl837030 isl83740 isl837030 qpsk 0 1 12 5.6000 to 79.3595 5.6000 to 79.3595 all payload rates: 3.0000 to 42.5140 3.0000 to 42.5140 8psk 1 1 12 8.4000 to 119.0392 8.4000 to 119.0392 16qam 2 3/4 2 8.4000 to 119.0392 8.4000 to 119.0392 7/8 6 9.8000 to 138.8791 9.8000 to 138.8791 1 12 11.2000 to 158.7189 11.2000 to 158.7189 32qam 4 4/5 3 11.2000 to 158.7189 11.2000 to 158.7189 9/10 8 12.6000 to 178.5588 12.6000 to 160.0000 3.0000 to 38.0953 1 12 14.0000 to 198.3987 14.0000 to 160.0000 3.0000 to 34.2857 64qam 6 5/6 4 14.0000 to 198.3987 n/a n/a 11/12 9 15.4000 to 218.2385 1 12 16.8000 to 238.0784 128qam 8 6/7 5 16.8000 to 238.0784
performance specifications isl837030, isl83740 8 fn8013.5 modulator performance specifications modulator input requirements modulator output electrical specifications 1 output levels are not guaranteed when using the modulator tuner. item description baseband amplitude imbalance < 0.1db after initial trim, over temperature and life < 0.2db typical without trim spectral flatness (relative to ideal rrc spectrum) +0.1db, -0.5db baseband phase imbalance <0.5 , over temperature and life i/q average group delay imbalance 0.3ns maximum residual output voltage noise floor (>100mhz) less than -110dbmv/hz rms differential i/q anti-alias filter low pass response 3-pole, -3db at 32.0mhz i/q ac coupling high pass response 1-pole, -3db at 75hz tx symbol timing jitter (1khz to baud/2) 1.0 rms, referred to symbol period spurious components (below 140mhz) dac aliasing component (15mbaud to 17.5mbaud, 29.75mbaud to 35mbaud) -55dbc or better dac aliasing component (other baud rates) -65dbc or better miscellaneous spurious components spurious outputs (above 140mhz) less than -80dbc item description input data byte clock phase noise evm and ber may be degraded if this parameter is exceeded. when integrated over an offset bandwidth of 500hz to half the byte rate frequency, then scaled proportionally to the symbol rate frequency. < (2.0 x ) rms, when integrated from 300hz to f baud f byte 2 f byte item description output signal type fully balanced differential, ac coupled baseband output level into recommended load 1 nominal: 1.9v p-p. maximum: 2.2v p-p baseband output adjust/resolution 1 programmable -4db to + 1.5db, in approximately 0.04db steps. baseband offset trim 1 programmable 31mv in 0.244mv steps into 1.2k ? load at +2.5v bias (offset adjustment of 0vdc to +5vdc through 95k ? connected to output). for details, see the programmer?s reference an9935. load impedance (required) 1.20k ? 20%, < 20pf, each leg to ground the modulator pulse shaping, interpolation, and analog anti-alias filtering have been designed to meet the requirements of applicable fcc, ic, itu, and etsi standard spectral masks. applicable standards: fcc 47cfr 101.111; etsi en 300-197, 198, 430, and 431; etsi en 301-128.
performance specifications isl837030, isl83740 9 fn8013.5 demodulator input requirements demodulator input electrical specifications item description symbol frequency error 200 ppm of symbol rate spectral slope error up to 2db average tilt across passband average i/q group delay imbalance < 6% of symbol period, up to 40mbaud < 1.5ns for 40mbaud to 42.5mbaud i/q group delay response flatness (p-p delay variation across 3db spectrum) carrier leakage component -30dbc or better for qpsk, 8psk, 16qam -35dbc or better for 32qam, 64qam, 128qam (64qam and 128qam available in isl83740 only) baseband source amplitude error < 1.0db maximum baseband source phase imbalance <5 maximum item description input signal type balanced differential, dc coupled input impedance balanced: 1.00k ? differential unbalanced : 1.00k ? in unbalanced mode, source impedances of both legs should be approximately equal to avoid dc offset at the adcs. matched source impedances of < 100 ? are recommended. baseband input level 1.00v p-p for full scale at adc baseband input bias current: source outputs must sink 0.4ma for 0.00vdc input source, each leg offset: < 10 a open circuit input bias voltage 600mvdc (baseband loopback off) input overload level approximately 2.5v p-p
performance specifications isl837030, isl83740 10 fn8013.5 demodulator performance specifications 1 the maximum acquisition and tracking rate range is less than 400khz when the baud rate is less than 6.6mbaud, as shown in figure 4. figure 4 acquisition/tracking range at low baud rates ber performance (typical) 1 performance is based on a standard setup using the evaluation platform?s vhf interface under typical operating conditions at baud rates > 10mbaud as defined in demodulator input requirements on page 9 . all loop bandwidths are set by default to accommodate severe mul tipath distortions. performance can be increased significantly by adjusting loop bandwidths for a less severe environment. performance is 0.5db to 1db better when using the evaluation platform?s h igh performance l-band interface. item description rx carrier tracking range 1 400khz rx carrier acquisition range 1 programmable from 50khz to 400khz in increments of 1khz. for details, see the programmer?s reference an9935. 100 150 200 250 300 350 400 450 345678 symbol rate (mbaud) max rxacqrange (khz) 64qam and 128qam available in isl83740 only. parameters eb/no conditions ber modulation type inner code rate 1.0e-8 ber qpsk 1 8.1db standard setup using low-cost vhf if interface loopback 1 8psk, 1 11.6db 16qam 1 12.2db 32qam 1 14.8db 64qam 1 18.7db 1.0e-10 ber 16qam 3/4 7.8db 7/8 9.0db 32qam 4/5 9.7db 9/10 11.4db 64qam 5/6 12.7db 11/12 15.0db 128qam 6/7 17.2db residual ber, fec disabled 32qam 1 ber < 1.0e-11 standard setup using low-cost vhf if interface loopback 1 no added noise 0 baseband loopback, no noise
performance specifications isl837030, isl83740 11 fn8013.5 controller parameters item description monitor and control (m&c) port ttl level uart, rxd, txd only, no handshake 115.2kbaud 8bits noparity 1 stop bit fpga configuration update can be performed via m&c port independent of application code update cannot be done during modem operation on-board flash memory holds up to four decimating matched filter configurations application code update can be performed via m&c port independent of fpga configuration update cannot be done during modem operation boot-loader write protected to ensure unconditional recovery. reset time from power up 8 seconds
isl837030, isl83740 12 fn8013.5 environmental & physical specifications reliability mtbf 457,000 hours (52 years) per bellcore standard tr-332 power supply requirements temperature and humidity tolerances board size and weight (excluding connectors) demodulator assp airflow requirements 1 included in isl83740eval/isl83700eval evaluation platform configurations. voltage current +5vdc 5% 100ma +3.3vdc 5% 5a -8.75vdc to -12vdc 100ma +8.75vdc to +12vdc 100ma environment operating storage temperature -40 cto85 c -50 cto150 c humidity (non-condensing) <95% operating humidity tolerance can be increased by conformal coating. 99% length and width 6? x 6? height on top 0.3? plus heatsink height on bottom 0.11? weight 5oz. aavid heatsink heatsink height for 85 coperation (4.3 c/w required) for 70 c operation (6.1 c/w required) unit 372024 1.100? 125 0 linear feet per minute 371924 1 0.550? 265 165 372824 0.230? 400 300
isl837030, isl83740 13 fn8013.5 physical interface definition the following figure highlights the board connectors: figure 5 modem pcba connectors pin 1 8-pin modulator baseband connector 8-pin demodulator baseband connector 2 4 6 80 1 3 5 79 2 4 6 8 1 3 5 7 bottom view actual connector pins 80-pin connector are on bottom pin 1 8-pin modulator baseband connector 8-pin demodulator baseband connector 80 78 76 2 79 77 75 1 top view 8 6 4 2 7 5 3 1 80-pin connector
physical interface definition isl837030, isl83740 14 fn8013.5 80-pin digital/power connector modem connector part #: samtec tsw-140-07-t-d suggested mating connector: samtec ssw-140-22-t-d the following figure shows the pin configuration for the 80-pin digital/power connector. for additional details, see the following pages. figure 6 digital/power connector pin configuration 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 +3.3 vdc din 0 2 4 6 mod _ dclk txd modem _ present 1 agc _ data agc _ clk agc _ sync demod _ lk d dmd _ psync 0 2 4 6 d aground - analog _ vdc reserved din din din +3.3 vdc irq +3.3 vdc +3.3 vdc ground +3.3 vdc dout dout dout dout ground reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 dground din 1 din 3 din 5 din 7 d mod _ psync reset rxd d modem _ present 2 d modem _ rdy +5 vdc dmd _ dclk d dmd _ dflag dout 1 3 5 7 dmd _ dataok aground + analog _ vdc analog _ agc ground ground ground ground dout dout dout reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
physical interface definition isl837030, isl83740 15 fn8013.5 power supply signals m&c port signals modulator data interface signals pin(s) signal name description characteristic 78 +analog_vdc positive analog voltage +8.75vdc to +12vdc 77 -analog_vdc negative analog voltage -8.75vdc to -12vdc 1 11 23 51 59 +3.3vdc digital voltage 5% 56 +5vdc 75 76 aground analog ground 2 12 24 52 57 60 71 dground digital ground pin(s) signal name description characteristic 22 rxd status data from modem (output) ttl v oh =2.4vminimum v ol =0.6vmaximum 21 txd control data to modem (input) ttl v ih =2.3vminimum v il =0.8vmaximum pin(s) signal name description characteristic 3 din0 data input lsb ttl v ih =2.3vminimum v il =0.8vmaximum 4 din1 data input 5 din2 6 din3 7 din4 8 din5 9 din6 10 din7 data input msb 13 mod_dclk byte rate input clock. data sampledonrisingedge. 14 mod_psync when in external sync byte mode, active high flag indicates sync byte location in input transport stream. when not used leave open or tie low.
physical interface definition isl837030, isl83740 16 fn8013.5 demodulator data interface signals pin(s) signal name description characteristic 63 dout0 data output lsb ttl v oh 2.4v minimum v ol 0.4v maximum 64 dout1 data output 65 dout2 66 dout3 67 dout4 68 dout5 69 dout6 70 dout7 data output msb 61 dmd_psync active high signal indicates sync byte is available on bus. 62 dmd_dflag active high signal indicates valid data is available on bus. low indicates reed solomon parity or sync byte is on bus. 58 dmd_dclk byte output clock. data transitions on falling edge. this clock is assp process clock gated when valid data is output from the assp. valid data includes sync and parity bytes. 72 dmd_dataok active high signal indicates presence of rs-correctable packet. indicates the current output packet contains no errors. 80 analog_agc a voltage representative of the digital value calculated by the assp. the assp averages the magnitude of the input baseband signal, subtracts that from a target value, and accumulates the results. range: 0vdc to 3.0vdc impedance: 100 ? current: 3ma maximum update rate: approximately every 2,000 symbols 49 agc_clk serial clock output. data transitions on rising edge, should be stored on the falling edge. ttl v oh 2.4v minimum v ol 0.4v maximum 53 agc_sync active low signal used to bound valid data out. 47 agc_data serial data, 12 bits agc, 4 bits padding. data transitions on rising edge of agc_clk .see agc timing on page 21 .
physical interface definition isl837030, isl83740 17 fn8013.5 miscellaneous signals reserved pin(s) signal name description characteristic 20 reset active low hard reset. resets processor and assps to their initial conditions. this signal is extended by 350ms by a device used to monitor vcc and the state of the reset signal. open drain v ih 2.0v minimum v il 0.8v maximum 5k pullup to 3.3v on modem 19 irq active low interrupt request indicates modem requires attention. when enabled this signal asserts, indicating that a fault condition exists on the modem. ttl v oh 2.4v minimum v ol 0.4v maximum 55 demod_lk demodulator lock indicator. low = lock 54 modem_rdy active high indicates modem is ready. indicates modem is available after power up or reset. typical time is less than 8 seconds after valid 3.3v or reset . 45 or 46 modem_present1 modem_present2 4.7k pullup to 3.3v use either 45 or 46; do not tie together. can be used for modem presence detect. pin(s) description 15-18 25-44 48 50 73-74 79 leave all unused pins unconnected. some are used for test and some are reserved for future expansion.
physical interface definition isl837030, isl83740 18 fn8013.5 8-pin baseband connectors modem connector part number: samtec tsw-104-07-t-d modulator analog baseband connector figure 7 modulator connector pin configuration demodulator analog baseband connector figure 8 demodulator connector pin configuration pin(s) signal name description characteristic 1 mod i+ i baseband analog output 1.9v p-p differential with 1.2k ? , < 20pf load 2 mod i- 5 mod q+ q baseband analog output 6 mod q- 3 4 7 8 gnd ground pin(s) signal name description characteristic 1 dmd i+ i baseband analog input 1.0v p-p nominal 1.0k ? , < 25pf load 2 dmd i- 5 dmd q+ q baseband analog input 6 dmd q- 3 4 7 8 gnd ground mod i- gnd mod q- gnd mod i+ gnd mod q+ gnd 2 4 6 8 1 3 5 7 dmd i- gnd dmd q- gnd dmd i+ gnd dmd q+ gnd 2 4 6 8 1 3 5 7
isl837030, isl83740 19 fn8013.5 data timing and packet definition modulator data input timing figure 9 modulator data input timing modulator packet definition external sync byte mode. 1 figure 10 modulator packet definition 1 when using internal sync byte mode, byte-wide data is input to the modulator at a constant rate defined by the configured data rate. reed solomon packetization is transparent to the input interface. symbol description min units tscf shift_clk clock period 50.0 nsec tscpw shift_clk pulse width 8.0 tddsu data setup time 12.0 tddhld data hold time 1.0 m od_dclk tddsu tscpw tddhld tscf m od_psync din [7..0] sync byte (1) data (223 bytes) reed solomon packet
data timing and packet definition isl837030, isl83740 20 fn8013.5 demodulator data output timing 1 the dmd_dclk is asynchronous to the output data rate and is a gated version of the demodulator?s process clock. its periodicity varies significantly based on symbol rate and decimating filter configurations. if a continuous output clock is desired, the user must provide some form of ?elastic buffer? external to the modem. figure 11 demodulator data output timing demodulator rs data packet definition 1 sixteen reed solomon parity bytes are output whether encoding is enabled or disabled. figure 12 demodulator data packet definition reed solomon (rs) packet size is calculated as follows: rs packet size = 1 sync byte + payload bytes + 16 rs parity bytes sync byte: (external sync mode) supplied by the host c onnected to the transmitting modem, (internal sync mode) supplied internally by the transmitting modem payload bytes: supplied by the host connected to the transmitting modem rs parity bytes: supplied internally by the transmitting modem an rs packet length of 240 = 1 sync byte + 223 payload bytes + 16 rs parity bytes. supported by external sync mode only. an rs packet length of 255 = 1 sync byte + 238 payload bytes + 16 rs parity bytes. supported by internal sync mode only. symbol description min max units tper dmd_dclk clock period note: worst case, assumes consecutive pulses are gated by the demodulator. 11.76 n/a nsec thpul dmd_dclk high width 3.7 n/a tdcf delay clock to dmd_dflag , dmd_psync -.05 2 tdcd delay clock to dout dout[7..0] tdcd d md_psync, d md_dflag, d md_dataok dmd_dclk 1 tdcf thpul tper dmd_psync dmd_dflag dout[7..0] sync byte (1) reed solomon parity 1 payload bytes d md_dataok valid packet
data timing and packet definition isl837030, isl83740 21 fn8013.5 agc timing figure 13 agc timing symbol description min max units tper agc_clk clock period, 50% 5% duty cycle 200 n/a nsec tsdly agc_sync delay from agc_clk 0 5 tddly agc_data delay from agc_clk 0 10 tupdate delay between updates 3.2 typical s // // / / // tddly ts d l y tper d11 (msb) d0 (lsb) d10 a gc_sync agc_clk agc_data ignore first 4 clock cycles d1 // tupdate tupdate
isl837030, isl83740 22 fn8013.5 mechanical drawings measurements are in inches. figure 14 modem pcba mechanical dimensions (top view) 5.616 2 .008 1 5.335 2 5.741 3 .308 1 7 7 5.741 8 2 8 tsw-140-07-t-d . 8 5 8 . 1 2 5 .175 .125 1 2 . 0 0 0 tsw-104-07-t-d samtec p/n 5.616 modem pcba 79 80 non-plated thru holes 4plc's .125 dia. samtec p/n . 000
isl837030, isl83740 23 fn8013.5 applications suggested baseband interfaces to the modem figure 15 modulator baseband interface to isl83740eval/isl83700eval platform this figure shows an if interface to an l-band daughterboard (included with the evaluation platform). vbias 4x 2.43k* i dac 0ma to 20ma 0ma to 20ma + - 1.8mf 1.8mf 124 0.1% 124 0.1% 143 0.1% 143 0.1% 0.42vdc 0.42vdc qdac 0ma to 20ma 0ma to 20ma + - 1.8mf 1.8mf 124 0.1% 124 0.1% 143 0.1% 143 0.1% 0.42vdc 0.42vdc 4x 2.43k* vbias -vr i-input q-input 2.2v p-p max 2.2v p-p max ad8346 direct u/c 12k 12k + - 12k 12k + - i level/bal ioffset q level/bal q offset opt. trimdacs 1 2 3 4 5 6 7 8 modem pcba *matched resistor networks recommended. 95k 95k
applications isl837030, isl83740 24 fn8013.5 . figure 16 unbalanced demodulator baseband interface, shorter runs figure 17 unbalanced demodulator baseband interface, longer runs modem pcba 49.9 1.05v p-p ich. 49.9 qch. 1.05v p-p 49.9 49.9 1 2 3 4 5 6 7 8 - ad8132 + - + 56.2 56.2 1.00k 1.00k - ad8132 + - + 56.2 56.2 1.00k 1.00k 1.00k 1.00k 1.00v p-p idata + - ich.adc 85msps 1.00v p-p 270nh, 5% 270nh, 5% 15pf 5% 68pf 2% 1.30k 15pf 5% 68pf 2% 270nh, 5% 270nh, 5% 1.30k for shorter runs + - qch.adc 85msps q da ta 1.00k 1.00k direct down convert baseband output amplifiers 2x 3.9pf 2x 3.9pf for longer runs modem pcba 1 2 3 4 5 6 7 8 - ad8132 + - + 56.2 56.2 1.00k 1.00k - ad8132 + - + 56.2 56.2 1.00k 1.00k 1.00k 270nh, 5% 270nh, 5% 15pf 5% 68pf 2% 1.30k 15pf 5% 68pf 2% 270nh, 5% 1.30k 2x 3.9pf 2x 3.9pf 1.00k 270nh, 5% 52.3 52.3 49.9 2.00v p-p ich. qch. 2.00v p-p 49.9 24.9 24.9 idata + - ich.adc 85msps 1.00v p-p 1.00k 1.00k + - qch.adc 85msps q dat a 1.00v p-p direct down convert baseband output amplifiers
isl837030, isl83740 25 fn8013.5 support note: in some cases, users may enter parameters outside of ranges listed in this document; however, only listed ranges are supported. related documentation for a list and description of documentation included with intersil commlink broadband products, see the readmefirst application note (an9940). additional documentation, product information, and press releases may be posted on the intersil web page: www.intersil.com/design/commlink/broadbandmodem.asp. release notes customer support intersil commlink broadband creates reference designs and related products for broadband wireless digital communications. if you have questions, comments, or suggestions concerning the product or this manual, please contact intersil customer support at www.intersil.com. isl83740 rev 5 the following is a change to the documentation to make it match the system. changed binary modulation type for 128qam to 8 (was 7). see modulation, inner code rates, and ranges on page 7 . isl837030 and isl83740 rev 4 added support for isl83740 functionality, higher data rates. see modulation, inner code rates, and ranges on page 7 . manual updated in other places where rates are listed to show which rates apply to isl83740 and isl837030. changed baseband output level into recommended load: nominal 1.9v p-p (was 1.95v p-p), maximum 2.2v p-p (was 2.45v p-p). changed baseband output adjust resolution: programmable +1.5db to -4db (was +2db to -4db). see modulator output electrical specifications on page 8 , figure 7 modulator connector pin configuration on page 18 (configuration), and figure 15 modulator baseband interface to isl83740eval/isl83700eval platform on page 23 . updated ber performance table to add new data rates/related information. see ber performance (typical) on page 10 . changed analog_agc current to be 3ma maximum (was 6ma maximum). see analog_agc on page 16. added acquisition and tracking range chart. see demodulator performance specifications on page 10. a reference to baud rates being > 10mbaud added to note under ber performance. see ber performance (typical) on page 10 . added support for mdleaver command (isl83740 only). see programmer?s reference an9935. isl837030 rev 3 added tupdate to agc timing diagram. changed tper min to be 200 (was 100). see agctimingonpage21 . rev 2 corrected thpul minimum from 5.29 to 3.7. ,page20 . updated demodulator airflow requirements. demodulator assp airflow requirements on page 12. corrected mtbf. reliability on page 12 rev 1 initial release all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, software and/or specific ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is beli eved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com

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